Along with evolution of the semiconductor packaging technology, various types of packages for semiconductor devices have been developed. For instance, Ball Grid Array (BGA) employs an advanced semiconductor packaging technique, which is characterized by disposing a semiconductor chip on a front side of a substrate, and mounting a plurality of array-arranged solder balls on a back side of the substrate via a self-alignment technique. This arrangement allows more input/output (I/O) connections to be accommodated on the same unit of area of a semiconductor chip carrier to satisfy the requirement for highly integrated chips, and the entire package unit can be bonded and electrically connected to an external printed circuit board via the solder balls.
Compared with the conventional wire-bonding technology, a flip-chip packaging technique introduced by IBM in early 1960s uses solder bumps, instead of gold wires, for electrical connection between a semiconductor chip and a substrate. The flip-chip packaging technique is advantageous in increasing packaging density and reducing package size. Moreover, the flip-chip packaging technique eliminates the use of relatively long metal wires, thereby improving electrical performances to satisfy the requirement of high-density and high-speed semiconductor devices.
In the current flip-chip packaging technique, a plurality of electrode pads are provided on a surface of a semiconductor IC (integrated circuit) chip, and corresponding contact pads are formed on a circuit board for carrying the semiconductor chip. Solder bumps or other conductive adhesive materials can be adequately disposed between the semiconductor chip and the circuit board so as to allow the semiconductor chip to be mounted on the circuit board in a face-down manner, such that the solder bumps or conductive adhesive materials provide electrical input/output (I/O) and mechanical connections between the semiconductor chip and the circuit board.
FIG. 1 shows a conventional flip-chip package. As shown in FIG. 1, a plurality of metallic bumps 11 are formed on electrode pads 12 of a semiconductor chip 13 respectively, and a plurality of pre-solder bumps 14 made of solder are formed on contact pads 15 of a circuit board 16 respectively. Under a reflow temperature condition sufficient for the pre-solder bumps 14 to melt, the pre-solder bumps 14 are reflowed to the corresponding metallic bumps 11 to form solder joints 17. Further, an organic underfill material 18 can be filled into a gap between the semiconductor chip 13 and the circuit board 16 and encapsulate the solder joints 17, so as to suppress a thermal expansion difference between the semiconductor chip 13 and the circuit board 16 and reduce stress applied to the solder joints 17.
Currently, pre-solder bumps are fabricated primarily by a stencil printing technique to deposit a solder material on contact pads of a circuit board. In fact, packages with miniaturized IC area and high-density multiple leads, such as a BGA package, chip size package (CSP), multi chip module (MCM) and so on, have become mainstream products in the package market due to dramatic growth of various portable electronic devices in communication, network and computer fields. Such packages usually cooperate with highly efficient semiconductor chips such as a microprocessor, chip set, graphic chip and so on to achieve higher speed operation. However, these package structures would reduce circuit trace width and pad size. When a pitch between adjacent pads is continuously decreased, since the pads are partly covered by an insulating protective layer located between the pads, the size of an exposed area of the pads becomes even smaller. This not only causes a positional alignment problem during subsequently forming pre-solder bumps, but also requires decrease of the size of stencil openings in the stencil printing technique, thereby leading to difficulty in depositing the solder material on the contact pads of the circuit board through such small stencil openings. As a result, the stencil printing technique would have low yield and becomes infeasible. Moreover, the stencil cost would be increased due to reduction in the pad size and pad pitch, making the fabrication cost raised. Furthermore, with the pad pitch being decreased, a contact area between the insulating protective layer and the circuit board is reduced, and thus adhesion therebetween becomes weakened. This further causes difficulty in fabricating fine-pitch pre-solder bumps and achieving good electrical connection.
Additionally, during fabrication of flip-chip semiconductor devices, similarly after integrated circuits are completely fabricated for a wafer, a under bump metallurgy (UBM) structure for carrying a metallic bump is formed on each of electrode pads of chips in the wafer. A singulation process is performed to cut the wafer into a plurality of semiconductor chips, and then the semiconductor chips can be mounted on and electrically connected to a circuit board in a flip-chip manner. During fabrication of the UBM structure and metallic bump, firstly, a passivation layer is formed on the wafer, with the electrode pads being exposed from the passivation layer. Then, the UBM structure comprising multiple metallic layers is formed on each of the electrode pads by sputtering and electroplating techniques. Afterwards, a photoresist layer is disposed on the passivation layer, and is preformed with a plurality of openings for exposing the UBM structures. A solder coating process is carried out to apply a solder material such as Sn/Pb alloy on the UBM structures via the openings of the photoresist layer by a screen-printing technique. Subsequently, a reflow process is performed to bond the solder material to the UBM structures respectively. After removing the photoresist layer, a second reflow process is performed to shape the solder material into spheres to form metallic bumps on the wafer, such that the metallic bumps can provide the electrical connection between the semiconductor chips and the circuit board.
For the flip-chip semiconductor device, it is necessary to form corresponding electrical connection elements (such as metallic bumps and pre-solder bumps) on the semiconductor chip and the corresponding circuit board respectively, and then perform packing and underfilling processes to accomplish the flip-chip package. Such method not only increases the fabrication processes and cost, but also raises the risk of degrading the reliability during fabrication. Moreover, according to the requirement of IC integration, the circuit size or the size and pitch of electrode pads and contact pads become gradually smaller, such that when electrical connection is to be subsequently formed for such fine circuits and such fine-pitch electrode pads and contact pads, precise positional alignment and fabrication are required but are actually very difficult to achieve.
Besides, when either the flip-chip packaging technique or the wire-bonding packaging technique is used, fabrication of the circuit board and packaging of the semiconductor chip must adopt different fabrication machines and processes, thereby making the fabrication processes complicated and the fabrication cost increased. In addition, during a molding process, the circuit board mounted with the semiconductor chip is placed in an encapsulation mold, and an epoxy resin material is injected into the mold to form an encapsulant for encapsulating the semiconductor chip. However, in practice, the mold may be limited by the design of the semiconductor package, thereby causing undesirable inaccuracy of size of a mold cavity and clamping positions, and a problem such as infirm clamping and so on. Moreover, when the resin material is injected into the mold, the encapsulant may easily flash to the surface of the circuit board. Such flashes not only impair the surface smoothness and the appearance of the semiconductor package, but also may contaminate bond pads on the circuit board for subsequently forming solder balls thereon, thereby degrading the electrical connection quality of the semiconductor package, and severely deteriorating the fabrication quality and product reliability of the semiconductor package.
Moreover, in general fabrication processes of semiconductor devices, firstly, suitable chip carriers for the semiconductor devices are made by a semiconductor chip carrier manufacturer (such as a circuit board manufacturer). Then, these semiconductor chip carriers are transferred to a semiconductor package manufacturer where chip-mounting, molding and ball-implanting processes are performed to form semiconductor packages having electronic functions required by clients. The fabrication processes involve different manufacturers (including the semiconductor chip carrier manufacture and the semiconductor package manufacturer), and thus are relatively complicated and cause difficulty in interface integration. If the clients wish to alter the function design, the associated changes and interface integration are even more complicated, thereby not providing sufficient flexibility in design alternation and economical benefits.